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Memory Wall

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Ahn J, Hong S, Yoo S, et al. A scalable processing-in-memory accelerator for parallel graph processing. In: Proceedings of 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA), Portland, 2015. 105–117 Kevin Skadron, Harry Douglas Forsyth Professor of Computer Science, heads up the UVA-led, nine-university research center that is creating the ultra-fast computing systems that pair data processing and memory in a single unit. I got value from all of the stories — fascinating to think about memories disappearing—re-appearing. Samira Khan, assistant professor of computer science, and Mircea Stan, Virginia Microelectronics Consortium Professor in the Charles L. Brown Department of Electrical and Computer Engineering, are on the team of UVA researchers leading the center since 2018.

In SRAM, the memory cell is a type of flip-flop circuit, usually implemented using FETs. This means that SRAM requires very low power when not being accessed, but it is expensive and has low storage density. To continue the innovations and break the memory wall, we need to rethink the design of AI models. There are several issues here. First, the current methods for designing AI models are mostly ad-hoc, and/or involve very simple scaling rules. For instance, recent large Transformer models are mostly just a scaled version of almost the same base architecture proposed in the original BERT model [22]. Second, we need to design more data efficient methods for training AI models. Current NNs require a huge amount of training data and hundreds of thousands of iterations to learn, which is very inefficient. Some might note that it is also different from how human brains learn, which often only require very few examples per concept/class. Third, the current optimization and training methods need a lot of hyperparameter tuning (such as learning rate, momentum, etc.), which often results in hundreds of trial and error sweeps to find the right setting to train a model successfully. As such, the training cost reported in Figure 1 is only a lower bound of the actual overhead, and the true cost is typically much higher. Fourth, the prohibitive size of the SOTA NN models makes their deployment for inference very challenging. This is not just restricted to models such as GPT-3. In fact, deploying large recommendation systems (which are similar to Transformers but which have much larger embedding and very few MLP layers afterwards [23]) that are used by hyperscalar companies is a major challenge. Finally, the design of hardware accelerators has been mainly focused on increasing peak compute with relatively less attention on improving memory-bound workloads. This has made it difficult both to train large models, as well as to explore alternative models, such as Graph NNs which are often bandwidth-bound and cannot efficiently utilize current accelerators. Bellis, Mary. "The Invention of the Intel 1103". Archived from the original on 2020-03-14 . Retrieved 2015-07-11. In general, the term RAM refers solely to solid-state memory devices (either DRAM or SRAM), and more specifically the main memory in most computers. In optical storage, the term DVD-RAM is somewhat of a misnomer since, unlike CD-RW or DVD-RW, it does not need to be erased before reuse. Nevertheless, a DVD-RAM behaves much like a hard disc drive if somewhat slower.a b c d "1970s: SRAM evolution" (PDF). Semiconductor History Museum of Japan . Retrieved 27 June 2019. Metal Oxide Semiconductor (MOS) Transistor Demonstrated". The Silicon Engine. Computer History Museum. Liu C, Sivasubramaniam A, Kandemir M (2004) Organizing the last line of defense before hitting the memory wall for CMPs. In: Proceedings of the 10th IEEE Symposium on High Performance Computer Architecture, Madrid, 14–18 Feb 2004. IEEE, Los Alamitos, pp 176–185 Iandola FN, Shaw AE, Krishna R, Keutzer KW. SqueezeBERT: What can computer vision teach NLP about efficient neural networks?. arXiv preprint arXiv:2006.11316. 2020 Jun 19.

The growth rate shown in Figure 2 is calculated by only considering the Transformer based models (blue circles), and not the recommendation systems.

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The demands for memory have only increased. DRAM now comprises 50% of the total server’s cost . This is the memory wall, and it has shown up in products. Comparing Nvidia’s 2016 P100 GPU to their 2022 H100 GPU that is just starting to ship, there is a 5x increase in memory capacity (16GB -> 80GB) but a 46x increase in FP16 performance (21.2 TFLOPS -> 989.5 TFLOPS). Scott, J.F. (2003). "Nano-Ferroelectrics". In Tsakalakos, Thomas; Ovid'ko, Ilya A.; Vasudevan, Asuri K. (eds.). Nanostructures: Synthesis, Functional Properties and Application. Springer Science & Business Media. pp.584–600 (597). ISBN 9789400710191. Gholami A, Kim S, Yao Z, Dong Z, Mahoney M, Keutzer K, A Survey of Quantization Methods for Efficient Neural Network Inference, arxiv preprint, arxiv:arXiv:2103.13630, 2021.

a b c "Spec Sheet for Toshiba "TOSCAL" BC-1411". Old Calculator Web Museum. Archived from the original on 3 July 2017 . Retrieved 8 May 2018. Gallagher, Sean (April 4, 2013). "Memory that never forgets: non-volatile DIMMs hit the market". Ars Technica. Archived from the original on July 8, 2017. When drawing time is up, ask the players to tape their scenes on the wall, forming a visual “memory cloud.” Japanese Technical Abstracts". Japanese Technical Abstracts. University Microfilms. 2 (3–4): 161. 1987. The announcement of 1M DRAM in 1984 began the era of megabytes. Rogers B, Krishna A, Bell G, Vu K, Jiang X, Solihin Y (2009) Scaling the bandwidth wall: challenges in and avenues for CMP scaling. In: Proceedings of the 36th International Symposium on Computer Architecture, Austin, 20–24 June 2009. IEEE/ACM, Los Alamitos/New York, pp 371–382I finished this story — uncertain —about how I felt and Luis Bunel’s words — were associated with my thoughts in regards to the first story. a b Shilov, Anton (July 19, 2017). "Samsung Increases Production Volumes of 8 GB HBM2 Chips Due to Growing Demand". AnandTech . Retrieved 29 June 2019. Yao Z, Dong Z, Zheng Z, Gholami A, Yu J, Tan E, Wang L, Huang Q, Wang Y, Mahoney MW, Keutzer K. HAWQV3: Dyadic Neural Network Quantization. arXiv preprint arXiv:2011.10680. 2020 Nov 20. Chen W H, Li K X, Lin W Y, et al. A 65 nm 1 Mb nonvolatile computing-in-memory ReRAM macro with sub-16 ns multiply-and-accumulate for binary DNN AI edge processors. In: Proceedings of IEEE International Solid-State Circuits Conference, San Francisco, 2018. 494–496 Part of this section is transcluded from Synchronous dynamic random-access memory. ( edit| history) Synchronous dynamic random-access memory (SDRAM)

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